Course Description
This course focuses on the integration of key fabrication processes to build complete CMOS devices, bridging the gap between individual process steps and full semiconductor device fabrication. It begins with bulk CMOS process integration, covering shallow trench isolation (STI), channel and well implants, lightly doped drains (LDD), salicidation, and metal gate technologies.
The course then explores FinFET process integration, including spacer lithography, advanced gate formation methods (gate-first and gate-last), and reliability considerations for next-generation devices.
In addition, the course introduces Technology Computer-Aided Design (TCAD) for process and device simulation, guiding participants through TCAD workflows, simulation file handling, and analysis techniques. Learners will also examine test structures and process parameter masks used for monitoring and optimizing fabrication outcomes.
By combining integration strategies, advanced device architectures, and simulation tools, this course equips participants with the skills to understand, evaluate, and optimize modern CMOS technology nodes.
What you'll learn
By the end of this course you will be able to:
• Describe bulk CMOS integration steps, including STI, well/channel implants, LDD, and salicidation, and their effects on device performance.
• Explain FinFET integration techniques, including spacer lithography, advanced gate formation (gate-first and gate-last), and key reliability concerns.
• Navigate TCAD tools, loading, running, and analyzing process and device simulations for fabrication workflows.
• Interpret simulation results to assess process variations and optimize device parameters.
• Evaluate test structures and process parameter masks, understanding their role in process monitoring and yield improvement.
Requirements
• Complete Course: CMOS Fabrication Fundamentals
• Complete Course: CMOS Deposition & Patterning Techniques
